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X24256ZI-2.5 Datasheet

  • X24256ZI-2.5

  • EEPROM

  • 18頁(yè)

  • ETC

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Preliminary
256K
X24256
400KHz 2-Wire Serial E
2
PROM
DESCRIPTION
32K x 8 Bit
FEATURES
鈥?400KHz 2-Wire Serial Interface
鈥擲chmitt Trigger Input Noise Suppression
鈥擮utput Slope Control for Ground Bounce
Noise Elimination
鈥?Longer Battery Life With Lower Power
鈥擜ctive Read Current Less Than 1mA
鈥擜ctive Write Current Less Than 3mA
鈥擲tandby Current Less Than 1
碌
A
鈥?1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
鈥?64 Byte Page Write Mode
鈥擬inimizes Total Write Time Per Word
鈥?Internally Organized 32K x 8
鈥?Bidirectional Data Transfer Protocol
鈥?Self-Timed Write Cycle
鈥擳ypical Write Cycle Time of 5ms
鈥?High Reliability
鈥擡ndurance: 100,000 Cycles
鈥擠ata Retention: 100 Years
鈥?8-Lead XBGA
鈥?8-Lead SOIC
鈥?14-Lead TSSOP
The X24256 is a CMOS Serial E
2
PROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Two device select inputs (S
0
鈥揝
1
) allow up to four
devices to share a common two wire bus.
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
FUNCTIONAL DIAGRAM
SERIAL E
2
PROM DATA
AND ADDRESS (SDA)
DATA REGISTER
Y DECODE LOGIC
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE PROTECT
CONTROL LOGIC
SERIAL E
2
PROM
ARRAY
32K x 8
SCL
PAGE
DECODE
LOGIC
S1
S0
DEVICE
SELECT
LOGIC
WP
WRITE VOLTAGE
CONTROL
漏
Xicor, 2000 Patents Pending
9800-5004.1 1/31/00 EP
Characteristics subject to change without notice.
1 of 18

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