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CY7C4201 Datasheet

  • CY7C4201

  • 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

  • Cypress

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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
(continued)
Programmable Almost Full Flag Timing
t
CLKH
WCLK
t
ENS
t
ENH
WEN1
Note
25
t
ENS
t
ENH
PAF
FULL
鈭?/div>
M+1 WORDS
IN FIFO
t
PAF
FULL
鈭?/div>
M WORDS
IN FIFO
[26]
t
SKEW2
[27]
t
PAF
t
CLKL
Note
24
WEN2
(if applicable)
RCLK
t
ENS
REN1,
REN2
t
ENS
t
ENH
Write Programmable Registers
t
CLK
t
CLKH
WCLK
t
ENS
WEN2/LD
t
ENS
WEN1
t
DS
D
0
鈥揇
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
t
DH
t
ENH
t
CLKL
Notes:
21. t
SKEW2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than t
SKEW2
, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n 鈥?1) words in the FIFO when PAE goes LOW.
24. If a Write is performed on this rising edge of the Write clock, there will be Full 鈥?(m 鈥?1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 64-m words for CY7C4421, 256 鈥?m words in FIFO for CY7C4201, 512 鈥?m words for CY7C4211, 1024 鈥?m words for CY7C4221, 2048 鈥?m words for CY7C4231,
4096 鈥?m words for CY7C4241, 8192 鈥?m words for CY7C4251.
27. t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *A
Page 12 of 18

CY7C4201 PDF文件相關(guān)型號

CY7C4211,CY7C4221,CY7C4231,CY7C4241,CY7C4251,CY7C4421

CY7C4201相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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