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CY7C4201 Datasheet

  • CY7C4201

  • 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

  • 331.33KB

  • Cypress

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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ...................................鈥?5
擄
C to +150
擄
C
Ambient Temperature with
Power Applied...............................................鈥?5
擄
C to +125
擄
C
Supply Voltage to Ground Potential ............... 鈥?.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... 鈥?.5V to +7.0V
DC Input Voltage............................................ 鈥?.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
[4]
Ambient
Temperature
0
擄
C to +70
擄
C
鈥?0
擄
C to +85
擄
C
V
CC
5V 鹵10%
5V 鹵10%
Pin Definitions
Pin
D
0鈥?
Q
0鈥?
WEN1
Name
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit Bus
Data Outputs for 9-bit Bus
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables Device for Read Operation
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the
FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into
the FIFO.
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
When OE is LOW, the FIFO鈥檚 data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO鈥檚 outputs are in High-Z (high-impedance) state.
Description
WEN2/LD Dual Write Enable 2
Mode Pin
Load
I
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
RCLK
Read Clock
I
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
Note:
4. T
A
is the 鈥渋nstant on鈥?case temperature.
Document #: 38-06016 Rev. *A
Page 6 of 18

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CY7C4211,CY7C4221,CY7C4231,CY7C4241,CY7C4251,CY7C4421

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