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CY7C375i Datasheet

  • CY7C375i

  • UltraLogic 128-Macrocell Flash CPLD

  • 263.44KB

  • Cypress

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USE ULTRA37000鈩?/div>
FOR ALL NEW DESIGNS
Switching Characteristics
Over the Operating Range
[13]
7C375i鈥?25
Parameter
t
PD
t
PDL
t
PDLL
t
EA
t
ER
t
WL
t
WH
t
IS
t
IH
t
ICO
t
ICOL
Description
Input to Combinatorial Output
[1]
Input to Output Through Transparent Input
or Output Latch
[1]
Input to Output Through Transparent Input
and Output Latches
[1]
Input to Output Enable
[1]
Input to Output Disable
Clock or Latch Enable Input LOW Time
[9]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output
[1]
Input Register Clock or Latch Enable to
Output Through Transparent Output Latch
[1]
Clock or Latch Enable to Output
[1]
Set-Up Time from Input to Clock or Latch
Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output
Delay (Through Memory Array)
[1]
Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
Set-Up Time from Input Through Trans-
parent Latch to Output Register Clock or
Latch Enable
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
Maximum Frequency with Internal
Feedback (Least of 1/t
SCS
, 1/(t
S
+ t
H
), or
1/t
CO
)
[9]
8
5.5
0
14
10
[9]
CY7C375i
7C375i鈥?00
Min.
Max.
12
15
16
16
16
3
3
2
2
7C375i鈥?3
7C374iL鈥?3
Min.
Max.
15
18
19
19
19
4
4
3
3
7C375i鈥?6
7C375iL鈥?6
Min.
Max.
20
22
24
24
24
5
5
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
26
ns
ns
Min.
Max.
10
13
15
14
14
Combinatorial Mode Parameters
Input Registered/Latched Mode Parameters
3
3
2
2
14
16
16
18
19
21
Ouptut Registered/Latched Mode Parameters
t
CO
t
S
t
H
t
CO2
t
SCS
6.5
6
0
16
12
7
8
0
19
15
8
10
0
24
10
ns
ns
ns
ns
ns
t
SL
10
12
15
20
ns
t
HL
0
0
0
0
ns
f
MAX1
125
100
83
66
MHz
f
MAX2
158.3
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
), 1/(t
S
+ t
H
), or 1/t
CO
)
Maximum Frequency with External
Feedback (Lesser of 1/(t
CO
+ t
S
) and 1/(t
WL
+ t
WH
,
Output Data Stable from Output Clock
Minus Input Register Hold Time for 7C37x
[9,
14]
143
125
100
MHz
f
MAX3
83.3
76.9
62.5
50
MHz
t
OH
鈥搕
IH
37x
0
0
0
0
ns
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03029 Rev. *A
Page 8 of 17

CY7C375i相關(guān)型號(hào)PDF文件下載

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  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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