鈥?/div>
The reference frequency divider for the synthesizer PLL
The timing for the IF counter
The free-running frequency adjustment of the stereo decoder VCO
The center frequency adjustment of the IF 鏗乴ters
7.5 PLL tuning system
The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz or a 13 MHz
reference frequency generated by the crystal oscillator or applied to the IC from an
external source. The synthesizer can also be clocked via pin XTAL2 at 6.5 MHz. The PLL
tuning system can perform an autonomous search tuning function.
7.6 RF AGC
The RF AGC prevents overloading and limits the amount of intermodulation products
created by strong adjacent channels.
7.7 IF 鏗乴ter
Fully integrated IF 鏗乴ter.
7.8 FM demodulator
The FM quadrature demodulator has an integrated resonator to perform the phase shift of
the IF signal.
7.9 Level voltage generator and analog-to-digital converter
The FM IF analog level voltage is converted to 4 bits digital data and output via the bus.
7.10 IF counter
The IF counter outputs a 7-bit count result via the bus.
7.11 Soft mute
The low-pass 鏗乴tered level voltage drives the soft mute attenuator at low RF input levels.
The soft mute function can be switched off via the bus.
7.12 MPX decoder
The PLL stereo decoder is adjustment-free. The stereo decoder can be switched to mono
via the bus.
TEA5767HN_4
漏 Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 鈥?20 February 2006
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