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MAX6956 Datasheet

  • MAX6956

  • " 2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Di...

  • 407.32KB

  • Maxim   Maxim

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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port LED Display Driver and I/O Expander
MAX6956
INTENSITY
TEST
CONFIGURATION
P4 TO P31
LED DRIVERS
OR GPIO
INTENSITY REGISTERS
TEST REGISTER
PORT REGISTERS
MASK REGISTER
LED DRIVERS AND GPIO
PORT CHANGE
DETECTOR
CONFIGURATION
REGISTERS
DATA
8
SEGMENT OR
GPIO DATA
8
R/W
CE
R/W
MAX6956
AD0
AD1
ADDRESS
MATCHER
COMMAND
REGISTER DECODE
7
8
8
DATA BYTE
COMMAND BYTE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7
7-BIT DEVICE ADDRESS
SDA
SCL
SLAVE ADDRESS BYTE
R/W
TO/FROM DATA REGISTERS
TO COMMAND REGISTERS
DATA BYTE
COMMAND BYTE
Figure 1. MAX6956 Functional Diagram
Shutdown mode is temporarily overridden by the dis-
play test function.
Serial Interface
Serial Addressing
The MAX6956 operates as a slave that sends and
receives data through an I
2
C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6956, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6956 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k鈩?
is required on SDA. The MAX6956 SCL line operates
only as an input. A pullup resistor, typically 4.7k鈩? is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6956
7-bit slave address plus R/
W
bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
7
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