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5962-87658012A Datasheet

  • 5962-87658012A

  • LIN CMOS DUAL DIFFERENTIAL COMPARATORS

  • TI

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TLC372
LinCMOS錚?DUAL DIFFERENTIAL COMPARATORS
SLCS114D 鈭?NOVEMBER 1983 鈭?REVISED APRIL 2004
electrical characteristics at specified free-air temperature, V
DD
= 5 V, T
A
= 25擄C (unless otherwise
noted)
PARAMETER
VIO
IIO
IIB
VICR
IOH
VOL
Input offset voltage
Input offset current
Input bias current
Common-mode input voltage range
High-level output current
Low-level output voltage
VID = 1 V,
VID = 鈭?1 V,
VOH = 5 V
IOL = 4 mA
0 to
VDD 鈭?
0.1
150
400
TEST CONDITIONS鈥?/div>
VIC = VICRmin,
See Note 4
TLC372Y
MIN
TYP
1
1
5
MAX
5
UNIT
mV
pA
pA
V
nA
mV
IOL
Low-level output current
VID = 鈭?1 V,
VOL = 1.5 V
6
16
mA
IDD
Supply current (two comparators)
VID = 1 V,
No load
150
300
碌A(chǔ)
鈥?All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-k鈩?resistor
between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
ICR
test, rather than changing the input voltages, to provide greater
accuracy.
5V
1V
5.1 k鈩?/div>
+
鈭?/div>
Applied VIO
Limit
VO
Applied VIO
Limit
鈭? V
+
鈭?/div>
5.1 k鈩?/div>
VO
(a) VIO WITH VIC = 0
(b) VIO WITH VIC = 4 V
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
5

5962-87658012A PDF文件相關(guān)型號(hào)

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