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Figure 21. QSPI Assembly-Code Timing
TMS320C3x to MAX186 Interface
Figure 22 shows an application circuit to interface the
MAX186/MAX188 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 23.
Use the following steps to initiate a conversion in the
MAX186/MAX188 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
CLKX and CLKR of the TMS320 are tied together with
the SCLK input of the MAX186/MAX188.
2) The MAX186/MAX188
CS
is driven low by the XF_
I/O port of the TMS320 to enable data to be clocked
into DIN of the MAX186/MAX188.
3) An 8-bit word (1XXXXX11) should be written to the
MAX186/MAX188 to initiate a conversion and place
the device into external clock mode. Refer to Table
2 to select the proper XXXXX bit values for your spe-
cific application.
4) The SSTRB output of the MAX186/MAX188 is moni-
tored via the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the MAX186/MAX188.
Figure 22. MAX186/MAX188 to TMS320 Serial Interface
XF
CLKX
CS
SCLK
TMS320C3x
CLKR
DX
DR
FSR
DIN
DOUT
SSTRB
MAX186
MAX188
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull
CS
high to disable the MAX186/MAX188 until
the next conversion is initiated.
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