= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186鈥?/div>
4.7碌F capacitor at VREF pin; MAX188鈥攅xternal reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External compensation, 4.7碌F
External Clock Frequency Range
ANALOG INPUT
Input Voltage Range,
Single-Ended and Differential
(Note 9)
Multiplexer Leakage Current
Input Capacitance
Unipolar, V
SS
= 0V
Bipolar, V
SS
= -5V
On/off leakage current, V
IN
= 鹵5V
(Note 6)
4.076
鹵0.01
16
4.096
鹵30
鹵30
鹵30
鹵30
2.5
0
4.7
0.01
0.01
鹵1.5
V
DD
+
50mV
200
12
V
DD
-
50mV
20
1.5
10
350
mV
碌F
碌F
%
4.116
30
MAX186_C
MAX186A, MAX186B,
MAX186_E
MAX186C
MAX186_M
MAX186D
Load Regulation (Note 7)
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
EXTERNAL REFERENCE AT VREF
(Buffer disabled, VREF = 4.096V)
Input Voltage Range
Input Current
Input Resistance
Shutdown VREF Input Current
Buffer Disable Threshold REFADJ
2.50
V
碌A(chǔ)
k鈩?/div>
碌A(chǔ)
V
0mA to 0.5mA output load
Internal compensation
External compensation
Internal compensation
External compensation
鹵50
鹵60
鹵80
ppm/擄C
0 to
VREF
鹵VREF/2
鹵1
碌A(chǔ)
pF
V
mA
Internal compensation (Note 6)
Used for data transfer only
0.1
0.1
10
t
CONV
t
AZ
10
<50
1.7
2.0
0.4
MHz
Internal clock
External clock, 2MHz, 12 clocks/conversion
5.5
6
1.5
10
碌s
碌s
ns
ps
MHz
SYMBOL
-3dB rolloff
CONDITIONS
MIN
TYP
4.5
800
MAX
UNITS
MHz
kHz
MAX186/MAX188
V
INTERNAL REFERENCE
(MAX186 only, reference buffer enabled)
T
A
= +25擄C
VREF Output Voltage
VREF Short-Circuit Current
VREF Tempco
_______________________________________________________________________________________
3
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