= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186鈥?/div>
4.7碌F capacitor at VREF pin; MAX188鈥攅xternal reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
Internal compensation mode
External compensation mode
MAX186
MAX188
MAX186
MAX188
2.4
0.8
0.15
V
IN
= 0V or V
DD
(Note 6)
V
DD
- 0.5
0.5
SHDN
= V
DD
SHDN
= 0V
SHDN
= open
SHDN
= open
-100
-4.0
1.5
2.75
100
V
DD
-1.5
4.0
鹵1
15
MIN
0
4.7
1.678
1.638
鹵50
鹵5
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREF
Reference-Buffer Gain
REFADJ Input Current
DIGITAL INPUTS (DIN, SCLK,
CS
,
SHDN
)
DIN, SCLK,
CS
Input High Voltage
DIN, SCLK,
CS
Input Low Voltage
DIN, SCLK,
CS
Input Hysteresis
DIN, SCLK,
CS
Input Leakage
DIN, SCLK,
CS
Input Capacitance
SHDN
Input High Voltage
SHDN
Input Low Voltage
SHDN
Input Current, High
SHDN
Input Current, Low
SHDN
Input Mid Voltage
SHDN
Voltage, Floating
SHDN
Max Allowed Leakage,
Mid Input
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
V
DD
V
SS
Operating mode
Positive Supply Current
I
DD
Fast power-down
Full power-down
Negative Supply Current
I
SS
Operating mode and fast power-down
Full power-down
5 鹵5%
0 or
-5 鹵5%
1.5
30
2
2.5
70
10
50
10
V
V
mA
碌A(chǔ)
碌A(chǔ)
V
OL
V
OH
I
L
C
OUT
I
SINK
= 5mA
I
SINK
= 16mA
I
SOURCE
= 1mA
CS
= 5V
CS
= 5V (Note 6)
4
鹵10
15
0.3
0.4
V
V
碌A(chǔ)
pF
V
INH
V
INL
V
HYST
I
IN
C
IN
V
INH
V
INL
I
INH
I
INL
V
IM
V
FLT
碌F
V/V
碌A(chǔ)
V
V
V
碌A(chǔ)
pF
V
V
碌A(chǔ)
碌A(chǔ)
V
V
nA
4
_______________________________________________________________________________________