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MAX186DC/D Datasheet

  • MAX186DC/D

  • 低功耗、8通道、串行12位ADC

  • 0頁

  • MAXIM   MAXIM

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Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V 鹵5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186鈥?/div>
4.7碌F capacitor at VREF pin; MAX188鈥攅xternal reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
Positive Supply Rejection
(Note 8)
Negative Supply Rejection
(Note 8)
SYMBOL
PSR
PSR
CONDITIONS
V
DD
= 5V 鹵5%; external reference, 4.096V;
full-scale input
V
SS
= -5V 鹵5%; external reference, 4.096V;
full-scale input
MIN
TYP
鹵0.06
鹵0.01
MAX
鹵0.5
鹵0.5
UNITS
mV
mV
MAX186/MAX188
Note 1:
Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX186 鈥?internal reference, offset nulled; MAX188 鈥?external reference (VREF = +4.096V), offset nulled.
Note 4:
Ground on-channel; sine wave applied to all off channels.
Note 5:
Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
Measured at V
SUPPLY
+5% and V
SUPPLY
-5% only.
Note 9:
The common-mode range for the analog inputs is from V
SS
to V
DD
.
TIMING CHARACTERISTICS
(V
DD
= 5V 鹵5%; V
SS
=0V or -5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
Fall to SSTRB Output Enable
(Note 6)
CS
Rise to SSTRB Output Disable
(Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
SYMBOL
t
AZ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
t
SDV
t
STR
t
SCK
C
LOAD
= 100pF
External clock mode only, C
LOAD
= 100pF
External clock mode only, C
LOAD
= 100pF
Internal clock mode only
0
C
LOAD
= 100pF
C
LOAD
= 100pF
C
LOAD
= 100pF
100
0
200
200
200
200
200
MAX18_ _C/E
MAX18_ _M
20
20
CONDITIONS
MIN
1.5
100
0
150
200
100
100
TYP
MAX
UNITS
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
_______________________________________________________________________________________
5

MAX186DC/D PDF文件相關(guān)型號

MAX186EVKIT,MAX187BC/D

MAX186DC/D 產(chǎn)品屬性

  • Maxim Integrated Products

  • 1

  • 8

  • SAR

  • 133 KSPs

  • 12 bit

  • Single Ended, Differential

  • 4-Wire (SPI, Microwire, QSPI, TMS320)

  • 4.096 V

  • 6 V

  • - 0.3 V

  • 640 mW

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