Low-Power, 8-Channel,
Serial 12-Bit ADCs
________________________________________________Pin Description (continued)
PIN
12
13
14
15
16
17
18
19
20
NAME
REFADJ
AGND
DGND
DOUT
SSTRB
DIN
CS
SCLK
V
DD
FUNCTION
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to
V
DD
.
Analog Ground. Also IN- Input for single-ended conversions.
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when
CS
is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when
CS
is high (external mode).
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless
CS
is low. When
CS
is high, DOUT
is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V 鹵5%
MAX186/MAX188
+5V
DOUT
DOUT
3k
CS
SCLK
DIN
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
18
19
17
10
1
2
3
4
5
6
7
8
13
3k
DGND
C
LOAD
C
LOAD
DGND
b. High-Z to V
OL
and V
OH
to V
OL
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
a. High-Z to V
OH
and V
OL
to V
OH
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
T/H
CLOCK
IN12-BIT
SAR
ADC OUT
REF
20k
A
鈮?/div>
1.65
15
16
DOUT
SSTRB
Figure 1. Load Circuits for Enable Time
+5V
3k
DOUT
DOUT
20
14
9
V
DD
DGND
V
SS
3k
DGND
a V
OH
to High-Z
C
LOAD
C
LOAD
DGND
b V
OL
to High-Z
REFADJ
VREF
12
11
+2.46V
REFERENCE
(MAX186)
+4.096V
MAX186
MAX188
Figure 2. Load Circuits for Disabled Time
Figure 3. Block Diagram
_______________________________________________________________________________________
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