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TPS61040 Datasheet

  • TPS61040

  • 采用 SOT-23 封裝用于 LCD 和白光 LED 的 28V 400mA 開關(guān)升壓轉(zhuǎn)...

  • 19頁

  • TI

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TPS61040
TPS61041
SLVS413B 鈥?OCTOBER 2002 鈥?REVISED MAY 2004
INPUT CAPACITOR SELECTION
For good input voltage filtering, low ESR ceramic capacitors are recommended. A 4.7 碌F ceramic input capacitor
is sufficient for most of the applications. For better input voltage filtering this value can be increased. Refer to
Table 2 and typical applications for input capacitor recommendations.
DIODE SELECTION
To achieve high efficiency a Schottky diode should be used. The current rating of the diode should meet the
peak current rating of the converter as it is calculated in the section peak current control. Use the maximum
value for I
LIM
for this calculation. Refer to Table 3 and the typical applications for the selection of the Schottky
diode.
Table 3. Recommended Schottky Diode for Typical LCD Bias Supply (see Figure 15)
DEVICE
REVERSE VOLTAGE
30 V
TPS61040/41
20 V
20 V
30 V
COMPONENT SUPPLIER
ON Semiconductor MBR0530
ON Semiconductor MBR0520
ON Semiconductor MBRM120L
Toshiba CRS02
High efficiency
COMMENTS
LAYOUT CONSIDERATIONS
Typical for all switching power supplies, the layout is an important step in the design; especially at high peak
currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems
and duty cycle jitter.
The input capacitor should be placed as close as possible to the input pin for good input voltage viltering. The
inductor and diode should be placed as close as possible to the switch pin to minimize the noise coupling into
other circuits. Since the feedback pin and network is a high impedance circit the feedback network should be
routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
Wide traces should be used for connections in bold as shown in Figure 15. A star ground connection or ground
plane minimizes ground shifts and noise.
L1
D1
V
O
C
FF
C
O
V
IN
V
IN
SW
FB
R1
C
IN
EN
GND
R2
Figure 15. Layout Diagram
13

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