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DSPIC33FJ64MC508 Datasheet

  • DSPIC33FJ64MC508

  • 342頁

  • MICROCHIP   MICROCHIP

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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
FWDT
Description
Watchdog Timer Postscaler bits
1111
= 1:32,768
1110
= 1:16,384
.
.
.
0001
= 1:2
0000
= 1:1
Motor Control PWM Module Pin mode
1
= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0
= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
Motor Control PWM High-side Polarity bit
1
= PWM module high-side output pins have active-high output polarity
0
= PWM module high-side output pins have active-low output polarity
Motor Control PWM Low-side Polarity bit
1
= PWM module low-side output pins have active-high output polarity
0
= PWM module low-side output pins have active-low output polarity
Alternate I
2
C鈩?pins
1 = I
2
C mapped to SDA1/SCL1 pins
0 = I
2
C mapped to ASDA1/SACL1 pins
[Note: This bit is only present in the dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]
Power-on Reset Timer Value Select bits
111
= PWRT = 128 ms
110
= PWRT = 64 ms
101
= PWRT = 32 ms
100
= PWRT = 16 ms
011
= PWRT = 8 ms
010
= PWRT = 4 ms
001
= PWRT = 2 ms
000
= PWRT Disabled
Background Debug Enable bit
1
= Device will reset in User mode
0
= Device will reset in Debug mode
Debugger/Emulator Enable bit
1
= Device will reset in Operational mode
0
= Device will reset in Clip-On Emulation mode
JTAG Enable bit
1
= JTAG enabled
0
= JTAG disabled
ICD Communication Channel Select bits
11
= Communicate on PGC1/EMUC1 and PGD1/EMUD1
10
= Communicate on PGC2/EMUC2 and PGD2/EMUD2
01
= Communicate on PGC3/EMUC3 and PGD3/EMUD3
00
= Reserved, do not use
Unimplemented (read as 鈥?鈥? write as 鈥?鈥?
Bit Field
WDTPOST
PWMPIN
FPOR
HPOL
FPOR
LPOL
FPOR
ALTI2C
FPOR
FPWRT<2:0>
FPOR
BKBUG
FICD
COE
FICD
JTAGEN
FICD
ICS<1:0>
FICD
鈥?/div>
All
DS70152D-page 44
Preliminary
漏
2007 Microchip Technology Inc.

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