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AM29LV160DB-120FC Datasheet

  • AM29LV160DB-120FC

  • Advanced Micro Devices [16 Megabit (2 M x 8-Bit/1 M x 16-Bi...

  • 1666.24KB

  • AMD

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RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin to V
IL
for at least a period of t
RP
,
the device
immediately terminates
any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
鹵0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
鹵0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a 鈥?鈥?(busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is 鈥?鈥?, the reset operation is
completed within a time of t
READY
(not during Embed-
ded Algorithms). The system can read data t
RH
after
the RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Am29LV160D
11

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