AC CHARACTERISTICS
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ7
High Z
VA
VA
t
OE
t
DF
Complement
Complement
True
Valid Data
High Z
DQ0鈥揇Q6
t
BUSY
RY/BY#
Status Data
Status Data
True
Valid Data
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ6/DQ2
t
BUSY
RY/BY#
High Z
VA
VA
VA
t
OE
t
DF
Valid Status
(first read)
Valid Status
(second read)
Valid Status
(stops toggling)
Valid Data
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 20.
Toggle Bit Timings (During Embedded Algorithms)
Am29LV160D
39