ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Word Programming Time
Chip Programming Time
(Note 3)
Byte Mode
Word Mode
Typ (Note 1)
0.7
25
5
7
11
7.2
150
210
33
21.6
Max (Note 2)
15
Unit
s
s
碌s
碌s
s
s
Excludes system level
overhead (Note 5)
Comments
Excludes 00h programming
prior to erasure (Note 4)
Notes:
1. Typical program and erase times assume the following conditions: 25
擄
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90擄C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
Input voltage with respect to V
SS
on all I/O pins
V
CC
Current
Min
鈥?.0 V
鈥?.0 V
鈥?00 mA
Max
12.5 V
V
CC
+ 1.0 V
+100 mA
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
C
IN
C
OUT
C
IN2
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
Test Setup
V
IN
= 0
V
OUT
= 0
V
IN
= 0
Typ
6
8.5
7.5
Max
7.5
12
9
Unit
pF
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25擄C, f = 1.0 MHz.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
125擄C
20
Years
Test Conditions
150擄C
Min
10
Unit
Years
44
Am29LV160D