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AM29LV160DB-120FC Datasheet

  • AM29LV160DB-120FC

  • Advanced Micro Devices [16 Megabit (2 M x 8-Bit/1 M x 16-Bi...

  • AMD

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DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV160D Device Bus Operations
DQ8鈥揇Q15
Addresses
(Note 1)
A
IN
A
IN
X
X
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
DQ0鈥?/div>
DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
D
IN
BYTE#
= V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
X
BYTE#
= V
IL
DQ8鈥揇Q14 = High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
X
Operation
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
CE#
L
L
V
CC
鹵
0.3 V
L
X
L
OE# WE# RESET#
L
H
X
H
X
H
H
L
X
H
X
L
H
H
V
CC
鹵
0.3 V
H
L
V
ID
Sector Unprotect (Note 2)
Temporary Sector
Unprotect
L
H
L
V
ID
V
ID
D
IN
D
IN
X
X
X
X
X
D
IN
High-Z
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
鹵
0.5 V, X = Don鈥檛 Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH
), A19:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the 鈥淪ector
Protection/Unprotection鈥?section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15鈥揇Q0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic 鈥?鈥? the device is in
word configuration, DQ15鈥揇Q0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic 鈥?鈥? the device is in byte
configuration, and only data I/O pins DQ0鈥揇Q7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8鈥揇Q14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
main at V
IH
. The BYTE# pin determines whether the de-
vice outputs array data in words or bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See 鈥淩eading Array Data鈥?for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
Am29LV160D
9

AM29LV160DB-120FC PDF文件相關(guān)型號(hào)

AM29LV160DB-120WCC

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