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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • 733.62KB

  • CIRRUS

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CS8415A
MUX2:0 - 7:1 S/PDIF Input Multiplexer Select Line Control
Default = 鈥?00鈥?/div>
000 - RXP0
001 - RXP1
010 - RXP2
011 - RXP3
100 - RXP4
101 - RXP5
110 - RXP6
111 - Reserved
8.3
7
0
Clock Source Control (04h)
6
RUN
5
0
4
0
3
0
2
0
1
0
0
0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8415A to be placed in a 鈥減owered down鈥? low
current consumption, state.
Default = 鈥?鈥?/div>
0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is
operational, allowing registers to be read or changed. Reading and writing the U and C data
buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8415A to begin
operation. All input clocks should be stable in frequency and phase when RUN is set to 1.
8.4
7
Serial Audio Output Port Data Format (06h)
6
SOSF
5
SORES1
4
SORES0
3
SOJUST
2
SODEL
1
SOSPOL
0
SOLRPOL
SOMS
SOMS - Master/Slave Mode Selector
Default = 鈥?鈥?/div>
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
SOSF - OSCLK frequency (for master mode)
Default = 鈥?鈥?/div>
0 - 64*Fs
1 - 128*Fs
SORES1:0 - Resolution of the output data on SDOUT
Default = 鈥?0鈥?/div>
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits,
the time slot normally occupied by the P bit is used to indicate the location of the block start,
21

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

CS8415A-CS相關(guān)型號(hào)PDF文件下載

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