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CS8421-DZZ Datasheet

  • CS8421-DZZ

  • Cirrus Logic [32-bit, 192 kHz Asynchronous Sample Rate Conv...

  • CIRRUS

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CS8421
MS_SEL pin
1.0 k鈩?鹵 1% to GND
1.96 k鈩?鹵 1% to GND
4.02 k鈩?鹵 1% to GND
8.06 k鈩?鹵 1% to GND
16.2 k鈩?鹵 1% to GND
1.0 k鈩?鹵 1% to VL
1.96 k鈩?鹵 1% to VL
4.02 k鈩?鹵 1% to VL
8.06 k鈩?鹵 1% to VL
Input M/S
Slave
Slave
Slave
Slave
Slave
Master (
128 x Fsi
)
Master (
256 x Fsi
)
Master (
384 x Fsi
)
Master (
512
x Fsi)
Output M/S
Slave
Master (
128 x Fso
)
Master (
256 x Fso
)
Master (
384
x Fso)
Master (
512
x Fso)
Slave
Slave
Slave
Slave
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL)
SAIF pin
1.0 k鈩?鹵 1% to GND
1.96 k鈩?鹵 1% to GND
4.02 k鈩?鹵 1% to GND
1.0 k鈩?鹵 1% to VL
1.96 k鈩?鹵 1% to VL
4.02 k鈩?鹵 1% to VL
Input Port Configuration
I虜S up to 32-bit data
Left Justified up to 32-bit data
Right Justified 16-bit data
Right Justified 20-bit data
Right Justified 24-bit data
Right Justified 32-bit data
Table 2. Serial Audio Input Port Startup Options (SAIF)
SAOF pin
1.0 k鈩?鹵 1% to GND
1.96 k鈩?鹵 1% to GND
4.02 k鈩?鹵 1% to GND
8.06 k鈩?鹵 1% to GND
16.2 k鈩?鹵 1% to GND
32.4 k鈩?鹵 1% to GND
63.4 k鈩?鹵 1% to GND
127.0 k鈩?鹵 1% to GND
1.0 k鈩?鹵 1% to VL
1.96 k鈩?鹵 1% to VL
4.02 k鈩?鹵 1% to VL
8.06 k鈩?鹵 1% to VL
16.2 k鈩?鹵 1% to VL
32.4 k鈩?鹵 1% to VL
63.4 k鈩?鹵 1% to VL
127.0 k鈩?鹵 1% to VL
Output Port Configuration
I虜S 16-bit data
I虜S 20-bit data
I虜S 24-bit data
I虜S 32-bit data
Left Justified 16-bit data
Left Justified 20-bit data
Left Justified 24-bit data
Left Justified 32-bit data
Right Justified 16-bit data
Right Justified 20-bit data
Right Justified 24-bit data
Right Justified 32-bit data
TDM Mode 16-bit data
TDM Mode 20-bit data
TDM Mode 24-bit data
TDM Mode 32-bit data
Table 3. Serial Audio Output Port Startup Options (SAOF)
DS641PP1
13

CS8421-DZZ 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

  • SMD/SMT

  • TSSOP-20

  • 74

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