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LT1167I Datasheet

  • LT1167I

  • Linear Technology [Single Resistor Gain Programmable, Preci...

  • LINER

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LT1167
BLOCK DIAGRAM
W
V
+
VB
+
A1
R3
400鈩?/div>
鈥揑N
2
Q1
R5
10k
R6
10k
6 OUTPUT
鈥?/div>
C1
R1
24.7k
V
鈥?/div>
R
G
1
R
G
8
V
+
VB
+
A2
R7
10k
R4
400鈩?/div>
+IN
3
Q2
鈥?/div>
C2
V
鈥?/div>
R2
24.7k
7
4
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
V
+
V
鈥?/div>
V
鈥?/div>
Figure 1. Block Diagram
THEORY OF OPERATIO
The LT1167 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.05% at G = 100) with only one external
resistor R
G
. The value of R
G
in parallel with R1 (R2)
determines the transconductance of the preamp stage. As
R
G
is reduced for larger programmed gains, the transcon-
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does not
drop proportional to gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor R
G
.
Since the current that flows through R
G
also flows through
R1 and R2, the ratios provide a gained-up differential volt-
age,G = (R1 + R2)/R
G
, to the unity-gain difference amplifier
A3. The common mode voltage is removed by A3, result-
ing in a single-ended output voltage referenced to the
voltage on the REF pin. The resulting gain equation is:
V
OUT
鈥?V
REF
= G(V
IN+
鈥?V
IN鈥?/div>
)
where:
G = (49.4k鈩?/ R
G
) + 1
solving for the gain set resistor gives:
R
G
= 49.4k鈩?/(G 鈥?1)
+
V
鈥?/div>
R8
10k
5 REF
1167 F01
鈥?/div>
A3
U
11

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