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LPC2880 Datasheet

  • LPC2880

  • Philips Semiconductors [16/32-bit ARM microcontrollers; 8 k...

  • 164.40KB

  • PHILIPS

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Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Programming the 鏗俛sh in a running application is accomplished via a register interface on
the APB bus. The 鏗俛sh module can generate an interrupt request when burning or erasing
is completed.
The 鏗俛sh memory contains a buffer to allow for faster execution. Information is read from
the 鏗俛sh 128 bits at a time. The buffer holds this entire amount, which can represent four
32-bit ARM instructions. These captured instructions can them be executed without 鏗俛sh
read delays, improving system performance.
6.4.1 Features
鈥?/div>
Flash access for processor execution and data read is via the AHB bus.
鈥?/div>
Flash programming in a running application is via an APB register interface.
鈥?/div>
Initial programming or reprogramming is can be accomplished from the USB port.
6.5 External memory controller
The LPC2880/LPC2888 External Memory Controller (EMC) is a multi-port memory
controller that supports asynchronous static memory devices such as RAM, ROM and
鏗俛sh, as well as dynamic memories such as Single Data Rate SDRAM. It complies with
ARM鈥檚 AMBA.
6.5.1 Features
鈥?/div>
Dynamic memory interface support including Single Data Rate SDRAM.
鈥?/div>
Asynchronous static memory device support including RAM, ROM, and 鏗俛sh, with or
without asynchronous page mode.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8-bit and 16-bit static memory support.
16-bit SDRAM memory support.
Static memory features include:
鈥?/div>
Asynchronous page mode read.
鈥?/div>
Programmable wait states.
鈥?/div>
Bus turnaround delay.
鈥?/div>
Output enable, and write enable delays.
鈥?/div>
Extended wait.
鈥?/div>
2 MB address range with three chip selects.
鈥?/div>
One chip select for synchronous memory and three chip selects for static memory
devices.
鈥?/div>
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
鈥?/div>
Dynamic memory self-refresh mode controlled by software.
鈥?/div>
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is
typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per device.
Note:
Synchronous static memory devices (synchronous burst mode) are not supported.
LPC2880_LPC2888_1
漏 Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 鈥?22 June 2006
16 of 34

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