2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 3V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 5V, T
A
= +25擄C.) (Note 1)
PARAMETER
Pullup to V+ INPUT1, INPUT2
IRQ/SEG9, SDA Output Low
Voltage
SDA Output Low Voltage
SYMBOL
I
PULLUP
V
OLBK
V
OL(SDA)
I
SINK
= 6mA, T
A
= -40擄C to +85擄C
I
SINK
= 4mA, T
A
= T
MIN
to T
MAX
I
SINK
= 6mA
CONDITIONS
MIN
TYP
26.5
0.4
0.4
0.4
MAX
UNITS
碌A(chǔ)
V
V
MAX6958/MAX6959
TIMING CHARACTERISTICS
(V+ = 3V to 5.5V, T
A
= T
MIN
to T
MAX
, Figure 1, unless otherwise noted.) (Note 1)
PARAMETER
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time (Repeated) START
Condition
Repeated START Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus
Line
SYMBOL
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F
t
SP
C
B
(Notes 2, 4)
(Notes 2, 4)
(Notes 2, 5)
(Note 6)
(Note 3)
100
1.3
0.6
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
50
400
300
300
250
1.3
0.6
0.6
0.6
0.9
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
碌s
碌s
碌s
碌s
碌s
ns
碌s
碌s
ns
ns
ns
ns
pF
Note 1:
All parameters tested at T
A
=+25擄C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL鈥檚 falling edge.
Note 4:
C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 5:
I
SINK
鈮?/div>
6mA. C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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