最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

登錄 免費注冊 首頁 | 行業(yè)黑名單 | 幫助
維庫電子市場網(wǎng)
技術交流 | 電路欣賞 | 工控天地 | 數(shù)字廣電 | 通信技術 | 電源技術 | 測控之家 | EMC技術 | ARM技術 | EDA技術 | PCB技術 | 嵌入式系統(tǒng)
驅(qū)動編程 | 集成電路 | 器件替換 | 模擬技術 | 新手園地 | 單 片 機 | DSP技術 | MCU技術 | IC 設計 | IC 產(chǎn)業(yè) | CAN-bus/DeviceNe

大蝦進來看看這個程序有警告怎么改正

作者:xing198200 欄目:EDA技術
大蝦進來看看這個程序有警告怎么改正
大蝦進來看看這個程序有警告怎么改正
這個程序編譯沒錯,有幾出警告,防真時有問題!,指點怎么去出警告,防真能進行!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity f_muxa is
PORT(sel8:in std_logic_vector(3 downto 0);
q8, q7, q6, q5, q4, q3, q2, q1:in std_logic_vector(3 downto 0);
romout:out std_logic_vector (17 downto 0));
end f_muxa;
architecture m of f_muxa is
signal ss:std_logic_vector(3 downto 0);
signal pp:std_logic_vector(24 downto 0);
begin
p1:PROCESS(sel8)
begin
case sel8 is
when "0000" =>ssssssssssssssssssssssssssssssssssppPpPpppppppPpPpppppPpPpppPpPpPpPPromout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout(17 downto 0)romout<="000000000000000000";
end case;
end PROCESS p3;
end m;
Warning: Ignored unnecessary INPUT pin 'q80'
Warning: Ignored unnecessary INPUT pin 'q70'
Warning: Ignored unnecessary INPUT pin 'q60'
Warning: Ignored unnecessary INPUT pin 'q50'
Warning: Ignored unnecessary INPUT pin 'q40'
Warning: Ignored unnecessary INPUT pin 'q30'
Warning: Ignored unnecessary INPUT pin 'q20'
Warning: Ignored unnecessary INPUT pin 'q10'
高人指點一下!!多謝噻!!

2樓: >>參與討論
delli
暈死了,寫的是蝦米。刻 亂了
 
3樓: >>參與討論
xing198200
重新發(fā)一下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity f_muxa is
PORT(sel8:in std_logic_vector(3 downto 0);
q8, q7, q6, q5, q4, q3, q2, q1:in std_logic_vector(3 downto 0);
romout:out std_logic_vector (17 downto 0));
end f_muxa;
architecture m of f_muxa is
signal ss:std_logic_vector(3 downto 0);
signal pp:std_logic_vector(24 downto 0);
begin
p1:PROCESS(sel8)
begin
case sel8 is
when "0000" =>ss<=q1;
when "0001" =>ss<=q2;
when "0010" =>ss<=q3;
when "0011" =>ss<=q4;
when "0100" =>ss<=q5;
when "0101" =>ss<=q6;
when "0110" =>ss<=q7;
when "0111" =>ss<=q8;
when "1000" =>ss<="0000";
when "1001" =>ss<="0000";
when "1010" =>ss<="0000";
when "1011" =>ss<="0000";
when "1100" =>ss<="0000";
when "1101" =>ss<="0000";
when "1110" =>ss<="0000";
when "1111" =>ss<="0000";
when others =>ss<="0000";
end case;
end PROCESS p1;
p2:PROCESS(ss)
begin
case ss is
when "0000"=>pp<="0000000000000000000000000";
when "0001"=>Pp<="0000000000000000000000000" ;
when "0010"=>Pp<="1111111111111111111100100";
when "0011"=>pp<="1111111111111111111100100";
when "0100"=>pp<="0000000000000000001101000";
when "0101"=>pp<="0000000000000000001101000";
when "0110"=>Pp<="0000000000000000001001100";
when "0111"=>Pp<="0000000000000000001001100";
when "1000"=>pp<="1111111111111111100100101";
when "1001"=>pp<="1111111111111111100100101";
when "1010"=>Pp<="1111111111111111100001001";
when "1011"=>Pp<="1111111111111111100001001";
when "1100"=>pp<="1111111111111111110001101";
when "1101"=>Pp<="1111111111111111110001101";
when "1110"=>Pp<="1111111111111111101110001";
when "1111"=>Pp<="1111111111111111101110001";
when others=>PP<="000000000000000000000000";
end case;
end PROCESS p2;
p3: PROCESS(sel8)
begin
case sel8 is
when "0000"=>romout(17 downto 0)<=pp(17 downto 0);
when "0001"=>romout(17 downto 0)<=pp(18 downto 1);
when "0010"=>romout(17 downto 0)<=pp(19 downto 2);
when "0011"=>romout(17 downto 0)<=pp(20 downto 3);
when "0100"=>romout(17 downto 0)<=pp(21 downto 4);
when "0101"=>romout(17 downto 0)<=pp(22 downto 5);
when "0110"=>romout(17 downto 0)<=pp(23 downto 6);
when "0111"=>romout(17 downto 0)<=pp(24 downto 7);
when "1000"=>romout(17 downto 0)<="000000000000000000";
when "1001"=>romout(17 downto 0)<="000000000000000000";
when "1010"=>romout(17 downto 0)<="000000000000000000";
when "1011"=>romout(17 downto 0)<="000000000000000000";
when "1100"=>romout(17 downto 0)<="000000000000000000";
when "1101"=>romout(17 downto 0)<="000000000000000000";
when "1110"=>romout(17 downto 0)<="000000000000000000";
when "1111"=>romout(17 downto 0)<="000000000000000000";
when others=>romout<="000000000000000000";
end case;
end PROCESS p3;
end m;

Warning: Ignored unnecessary INPUT pin 'q80'
Warning: Ignored unnecessary INPUT pin 'q70'
Warning: Ignored unnecessary INPUT pin 'q60'
Warning: Ignored unnecessary INPUT pin 'q50'
Warning: Ignored unnecessary INPUT pin 'q40'
Warning: Ignored unnecessary INPUT pin 'q30'
Warning: Ignored unnecessary INPUT pin 'q20'
Warning: Ignored unnecessary INPUT pin 'q10'



4樓: >>參與討論
delli
恩,你的器件沒設置吧?要那么多的管腳的器件很難得啊,呵呵。
 
參與討論
昵稱:
討論內(nèi)容:
 
 
相關帖子
verilog 寄存器定義 & 賦值?
請各位前輩幫我看看下面的程序……
兩片7128可以實現(xiàn)菊花鏈的連接嗎?
一段出錯的程序???
請問,MAX-plusII和QuartusII4.2能不能同時用一個下載線?
免費注冊為維庫電子開發(fā)網(wǎng)會員,參與電子工程師社區(qū)討論,點此進入


Copyright © 1998-2006 udpf.com.cn 浙ICP證030469號