|
|||||||||||
| 技術(shù)交流 | 電路欣賞 | 工控天地 | 數(shù)字廣電 | 通信技術(shù) | 電源技術(shù) | 測(cè)控之家 | EMC技術(shù) | ARM技術(shù) | EDA技術(shù) | PCB技術(shù) | 嵌入式系統(tǒng) 驅(qū)動(dòng)編程 | 集成電路 | 器件替換 | 模擬技術(shù) | 新手園地 | 單 片 機(jī) | DSP技術(shù) | MCU技術(shù) | IC 設(shè)計(jì) | IC 產(chǎn)業(yè) | CAN-bus/DeviceNe |
新手請(qǐng)教,關(guān)于synplify的安裝 |
| 作者:huibaggio 欄目:EDA技術(shù) |
我加載license時(shí)總是出現(xiàn)如下錯(cuò)誤(附圖)7.6版的,請(qǐng)高手指點(diǎn) license.txt文件如下 #Synplicity License File, Generate by ROR Team. #For EVALUATION ONLY. If you like this SOFTWARE, BUY it! #Notes: This license is invalid, must work with the PATCH! FEATURE amplify synplctyd 2004.090 1-jan-2020 12345678901234567890 \ VENDOR_STRING=cynapps,modular,nosetback,amplify,multirun,pro,floorplanner,partioner,partitioner,quick,fsmexpl,batch,analyst,fpga,fsm,vhdl,verilog,tcl,editor,actel,ALTERA,LATTICE,LUCENT,quicklogic,XILINX,triscend,CYPRESS \ HOSTID=001122334455 NOTICE=ROR ck=118 SIGN=0 FEATURE synplifyasic synplctyd 2004.99999 1-jan-2020 uncounted \ VENDOR_STRING=amplify,analyst,batch,floorplanner,fpga,fsm,fsmexpl,modular,multirun,nosetback,partioner,partitioner,pro,quick,cynapps \ HOSTID=001122334455 NOTICE=ROR ck=55 SIGN=0 FEATURE synplify synplctyd 2004.99999 1-jan-2020 uncounted \ VENDOR_STRING=amplify,analyst,batch,floorplanner,fpga,fsm,fsmexpl,modular,multirun,nosetback,partioner,partitioner,pro,quick,fixgatedclocks,jobLaunch,preprocessor,cynapps,amplifyAsic,wan \ HOSTID=001122334455 NOTICE=ROR ck=22 SIGN=0 FEATURE synplifyaxis synplctyd 2004.99999 1-jan-2020 uncounted \ VENDOR_STRING=amplify,analyst,batch,floorplanner,fpga,fsm,fsmexpl,modular,multirun,nosetback,partioner,partitioner,pro,quick,fixgatedclocks,jobLaunch,preprocessor,cynapps,amplifyAsic,wan \ HOSTID=001122334455 NOTICE=ROR ck=65 SIGN=0 FEATURE synplifypro synplctyd 2004.99999 1-jan-2020 uncounted \ VENDOR_STRING=amplify,analyst,batch,floorplanner,fpga,fsm,fsmexpl,modular,multirun,nosetback,partioner,partitioner,pro,quick,fixgatedclocks,jobLaunch,preprocessor,cynapps,amplifyAsic,wan \ HOSTID=001122334455 NOTICE=ROR ck=124 SIGN=0 |
| 2樓: | >>參與討論 |
| 作者: huibaggio 于 2006/3/24 23:05:00 發(fā)布:
附圖在此
|
|
|
|
| 免費(fèi)注冊(cè)為維庫(kù)電子開發(fā)網(wǎng)會(huì)員,參與電子工程師社區(qū)討論,點(diǎn)此進(jìn)入 |
Copyright © 1998-2006 udpf.com.cn 浙ICP證030469號(hào) |