VHDL編譯有錯(cuò)，求助

作者：jsjdzwj　欄目：EDA技術(shù)

VHDL編譯有錯(cuò)，求助
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.All;
USE IEEE.Std_Logic_Arith.All;
USE IEEE.Std_Logic_Unsigned.All;

ENTITY ARM_Control IS
PORT
(
    DataIN:IN Std_Logic_Vector(2 DOWNTO 0);
    CLK:IN Std_Logic;
    DataOUT0,DataOUT1,DataOUT2,DataOUT3,DataOUT4,DataOUT5,DataOUT6,DataOUT7:BUFFER Std_Logic
);
END;

ARCHITECTURE Behavior OF ARM_Control IS
SIGNAL firstTime:Integer RANGE 0 TO 2:=0;
BEGIN
    IF firstTime=0 THEN
        DataOUT0<=1;
        DataOUT1<=1;
        DataOUT2<=1;
        DataOUT3<=1;
        DataOUT4<=1;
        DataOUT5<=1;
        DataOUT6<=1;
        DataOUT7<=1;
        firstTime<=1;
    END IF;

    PROCESS(CLK)
    BEGIN
        IF rising_edge(CLK) THEN
            CASE DataIN IS
                WHEN "000"=>DataOUT0<=NOT DataOUT0;
                WHEN "001"=>DataOUT1<=NOT DataOUT1;
                WHEN "010"=>DataOUT2<=NOT DataOUT2;
                WHEN "011"=>DataOUT3<=NOT DataOUT3;
                WHEN "100"=>DataOUT4<=NOT DataOUT4;
                WHEN "101"=>DataOUT5<=NOT DataOUT5;
                WHEN "110"=>DataOUT6<=NOT DataOUT6;
                WHEN "111"=>DataOUT7<=NOT DataOUT7;
            END CASE;
        END IF;
    END PROCESS;
END;


郁悶，找不出錯(cuò)誤

2樓：	>>參與討論
作者： jsjdzwj 于 2006/4/8 22:31:00 發(fā)布：有三個(gè)錯(cuò)

3樓：	>>參與討論
作者： zxq916 于 2006/4/11 16:37:00 發(fā)布：呵 IF語句必須放在進(jìn)程里才行!

4樓：

>>參與討論

作者： zxq916 于 2006/4/11 16:43:00 發(fā)布：

正確代碼!
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.All;
USE IEEE.Std_Logic_Arith.All;
USE IEEE.Std_Logic_Unsigned.All;

ENTITY ARM_Control IS
PORT
(
    DataIN:IN Std_Logic_Vector(2 DOWNTO 0);
    CLK:IN Std_Logic;
    DataOUT0,DataOUT1,DataOUT2,DataOUT3,DataOUT4,DataOUT5,DataOUT6,DataOUT7:BUFFER Std_Logic
);
END;

ARCHITECTURE Behavior OF ARM_Control IS
SIGNAL firstTime:Integer RANGE 0 TO 2:=0;

BEGIN
    PROCESS(CLK)
    BEGIN
        IF rising_edge(CLK) THEN
         IF firstTime=0 THEN
                DataOUT0<='1';
               DataOUT1<='1';
               DataOUT2<='1';
              DataOUT3<='1';
              DataOUT4<='1';
                DataOUT5<='1';
                DataOUT6<='1';
                DataOUT7<='1';
                firstTime<=1;
            END IF;
        CASE DataIN IS
                WHEN "000"=>DataOUT0<=NOT DataOUT0;
               WHEN "001"=>DataOUT1<=NOT DataOUT1;
               WHEN "010"=>DataOUT2<=NOT DataOUT2;
               WHEN "011"=>DataOUT3<=NOT DataOUT3;
               WHEN "100"=>DataOUT4<=NOT DataOUT4;
               WHEN "101"=>DataOUT5<=NOT DataOUT5;
               WHEN "110"=>DataOUT6<=NOT DataOUT6;
               WHEN others=>DataOUT7<=NOT DataOUT7;
        END CASE;
        END IF;
    END PROCESS;
END;

參與討論

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VHDL編譯有錯(cuò)，求助

VHDL編譯有錯(cuò)，求助