鈥?/div>
鈥?Low operating power
鈥?Active = 195 mA (typical)
鈥?Standby = 0.05 mA (typical)
鈥?Fully synchronous interface for easier operation
鈥?Burst counters increment addresses internally
鈥?Shorten cycle times
鈥?Minimize bus noise
鈥?Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Automatic power-down
Commercial temperature range
Available in 100-pin TQFP
Pin-compatible and functionally equivalent to
IDT709079
Logic Block Diagram
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
FT/Pipe
L
[2]
0/1
1
0
0
1
0/1
FT/Pipe
R
[2]
8/9
8/9
I/O
0L
鈥揑/O
7/8L
I/O
Control
15
I/O
0R
鈥揑/O
7/8R
I/O
Control
15
A
0
鈥揂
14L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
鈥揂
14R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
鈥揑/O
7
for x8 devices; I/O
0
鈥揑/O
8
for x9 devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06049 Rev. *A
Revised December 27, 2002