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CY7C197D Datasheet

  • CY7C197D

  • 256K (256K x 1) Static RAM

  • 0頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C197D
256K (256K x 1) Static RAM
Features
鈥?Pin- and function-compatible with CY7C197B
鈥?High speed
鈥?t
AA
= 10 ns
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?I
CC
= 60 mA @ 10 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 3 mA
鈥?TTL-compatible inputs and outputs
鈥?Data retention at 2.0V
鈥?Automatic power-down when deselected
鈥?Available in Pb-Free Packages
Functional Description
[1]
The CY7C197D is a high-performance CMOS static RAM
organized as 256K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197D has an automatic power-down
feature, reducing the power consumption when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (D
IN
) is written into the memory location specified on
the address pins (A
0
through A
17
).
Reading the device is accomplished by taking chip enable
(CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data output (D
OUT
) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197D is available in standard 24-Lead DIP and SOJ
Pb-Free Packages.
Logic Block Diagram
DI
Pin Configurations
DIP/SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
1
24
2
23
22
3
4
21
5
20
7C197D
19
6
18
7
8
17
9
16
10
15
14
11
12
13
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
D
IN
CE
INPUT BUFFER
A
13
A
14
A
15
A
16
A
17
A
0
A
1
A
2
A
3
A
4
ROW DECODER
1024 x 256
ARRAY
SENSE AMPS
DO
COLUMN
DECODER
POWER
DOWN
CE
D
OUT
WE
GND
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
WE
Selection Guide
CY7C197D-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
10
60
3
CY7C197D-12
12
50
3
CY7C197D-15
15
40
3
Note:
1. For guidelines on SRAM system design, please refer to the 鈥淪ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05458 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 11, 2005

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CY7C197D相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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