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廬

ISL6505

Data Sheet

January 2004

FN9109.2

Multiple Linear Power Controller with

ACPI Control Interface

The ISL6505 complements other power building blocks

(voltage regulators) in ACPI-compliant designs for

microprocessor and computer applications. The IC

integrates three linear controllers/regulators, switching,

monitoring and control functions into a 20-pin wide-body

SOIC or 20-pin QFN (also known as MLF) 5x5 package.

The ISL6505鈥檚 operating mode (active or sleep outputs) is

selectable through two digital control pins, S3 and S5.

One linear controller generates the 3.3V

DUAL

/3.3V

SB

voltage plane from the ATX supply鈥檚 5V

SB

output, powering

the south bridge and the PCI slots through an external NPN

pass transistor during sleep states (S3, S4/S5). In active

state (during S0 and S1/S2), the 3.3V

DUAL

/3.3V

SB

linear

regulator uses an external N-channel pass MOSFET to

connect the outputs directly to the 3.3V input supplied by an

ATX power supply, for minimal losses. The

3.3V

DUAL

/3.3V

SB

output is active for as long as the ATX 5V

SB

voltage is applied to the chip.

A controller powers up the 5V

DUAL

plane by switching in the

ATX 5V output through an NMOS transistor in active states,

or by switching in the ATX 5V

SB

through a PMOS (or PNP)

transistor in S3 sleep state. In S4/S5 sleep states, the

ISL6505 5V

DUAL

output is either shut down or stays on,

based on the state of the EN5 pin.

An internal linear regulator supplies the 1.2V for the voltage

identification circuitry (VID) only during active states (S0 and

S1/S2), and uses the 3V3 pin as input source for its internal

pass element.

A linear controller generates V

OUT1

from the

3.3V

DUAL

/3.3V

SB

voltage plane, using an external NFET.

The voltage is user-programmable to values between 1.2V

and 1.5V, using an external resistor divider. The mode is

user-selectable with the LAN pin; a logic high (or open)

selects the 10/100 LAN mode, where V

OUT1

is always on

(S0-S5); a logic low selects the Gigabit Ethernet mode,

where V

OUT1

is only on during active modes (S0-S2).

Features

鈥?Provides four ACPI-Controlled Voltages

- 5V

DUAL

USB/Keyboard/Mouse

- 3.3V

DUAL

/3.3V

SB

PCI/Auxiliary/LAN

- 1.2V

VID

Processor VID Circuitry

- V

OUT1

(1.2V - 1.5V programmable) LAN/Ethernet

鈥?Excellent Output Voltage Regulation

- All Outputs:

鹵2.0%

over temperature (as applicable)

鈥?Small Size; Very Low External Component Count

鈥?Undervoltage Monitoring of All Outputs with Centralized

FAULT Reporting and Temperature Shutdown

鈥?QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

鈥?Lead-Free Available as an Option

Applications

鈥?ACPI-Compliant Power Regulation for Motherboards

Ordering Information

TEMP.

PART NUMBER RANGE (擄C)

ISL6505CB

ISL6505CR

ISL6505CRZ

(Note 1)

ISL6505CRZ-T

(Note 1)

ISL6505EVAL1

ISL6505EVAL2

NOTE:

1. Intersil Lead-Free products employ special lead-free material sets;

molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

lead-free soldering operations. Intersil Lead-Free products are

MSL classified at lead-free peak reflow temperatures that meet or

exceed the lead-free requirements of IPC/JEDEC J Std-020B.

0 to 70

0 to 70

0 to 70

0 to 70

PACKAGE

20 Ld Wide SOIC

20 Ld 5x5 QFN

20 Ld 5x5 QFN

(Lead-Free)

PKG.

DWG. #

M20.3

L20.5x5

L20.5x5

20 Ld 5x5 QFN

L20.5x5

Tape & Reel (Lead-Free)

Evaluation Board (SOIC)

Evaluation Board (QFN)

Pinouts

- See page 6.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

|

Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright 漏 Intersil Americas Inc. 2004. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

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