TC51WHM516AXBN65,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WHM516AXBN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as
2,097,152 words by 16 bits. Using Toshiba鈥檚 CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device operates single power supply. The device also features SRAM-like
W/R timing whereby the device is controlled by CE1 , OE , and WE on asynchronous. The device has the page
access operation. Page size is 8 words. The device also supports deep power-down mode, realizing low-power
standby.
FEATURES
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Organized as 2,097,152 words by 16 bits
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Page read operation by 8 words
Logic compatible with SRAM R/W ( WE ) pin
Standby current
Standby
70
碌A(chǔ)
Deep power-down standby
5
碌A(chǔ)
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Access Times:
TC51WHM516AXBN
65
Access Time
CE1
Access Time
70
70 ns
70 ns
25 ns
30 ns
65 ns
65 ns
25 ns
30 ns
OE
Access Time
Page Access Time
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Package:
P-TFBGA48-0607-0.75AZ (Weight:
g typ.)
PIN ASSIGNMENT
(TOP VIEW)
1
A
B
C
D
E
F
G
H
2
OE
UB
I/O11
I/O12
I/O13
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
I/O2
I/O4
I/O5
I/O6
6
CE2
I/O1
I/O3
VDD
VSS
I/O7
I/O8
A20
PIN NAMES
A0 to A20
A0 to A2
Address Inputs
Page Address Inputs
LB
I/O9
I/O10
VSS
VDD
I/O1 to I/O16 Data Inputs/Outputs
CE1
Chip Enable Input
Chip select Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power
Ground
No Connection
CE2
WE
OE
I/O15 I/O14
I/O16
A18
A19
A8
WE
A11
LB ,
UB
V
DD
GND
NC
(FBGA48)
2002-08-22
1/11
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