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CY7C197D Datasheet

  • CY7C197D

  • 256K (256K x 1) Static RAM

  • 0頁

  • CYPRESS

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PRELIMINARY
Thermal Resistance
[4]
Parameter
螛
JA
螛
JC
Description
Thermal Resistance
(Junction to Ambient)
[4]
Thermal Resistance
(Junction to Case)
[4]
Test Conditions
Still Air, soldered on a 3 脳 4.5 inch, two-layer
printed circuit board
CY7C197D
All-Packages
TBD
TBD
Unit
擄C/W
擄C/W
AC Test Loads and Waveforms
[5]
10-ns Device
OUTPUT
50
鈩?/div>
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
12, 15 -ns Devices
Z = 50鈩?/div>
ALL INPUT PULSES
3.0V
10%
< t
r
R1 480
鈩?/div>
High-Z characteristics:
R1 480
鈩?/div>
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255鈩?/div>
5 pF
INCLUDING
JIG AND
SCOPE
R2
255鈩?/div>
90%
90%
10%
< t
r
30 pF*
GND
(a)
Equivalent to:
TH脡VENIN EQUIVALENT
167鈩?/div>
OUTPUT
1.73V
5V
OUTPUT
(b)
(c)
Switching Characteristics
Over the Operating Range
[6]
7C197D-10
Parameter
Read Cycle
t
power[7]
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
t
SCE
t
HA
t
SA
t
WC
t
AW
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[8]
CE HIGH to High
Z
[8, 9]
0
10
8
0
0
10
7
9
0
0
12
9
CE LOW to Power-Up
CE HIGH to Power-Down
CE LOW to Write End
Address Hold from Write End
Address Set-Up to Write Start
Write Cycle Time
Address Set-Up to Write End
3
5
0
12
10
0
0
15
10
3
10
3
5
0
15
100
10
10
3
12
3
7
100
12
12
3
15
100
15
15
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C197D-12
Min.
Max.
7C197D-15
Min.
Max.
Unit
Write Cycle
[10]
Notes:
5. t
r
= < 3 ns for all speeds.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured
鹵200
mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05458 Rev. *C
Page 3 of 8

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CY7C197D相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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